The present invention relates to the field of processor performance instrumentation, and more particularly to multiplexing multiple performance indicators during processor performance instrumentation.
A computer processor, such as a central processing unit, performs instructions under the direction of software programs. These instructions include loading memory, accessing cache, etc., and they consume processor resources. It is useful for computer software testers to measure how often the processor performs instructions under the direction of a program in order to measure the performance of the program. As a result, processor designers include hardware xe2x80x9ccountersxe2x80x9d in the processor that count the number of times the processor performs specific instructions or the number of times a particular event occurs. These counters are often called xe2x80x9cPerformance Instrumentation Counters,xe2x80x9d and the instructions or events they count, or measure, are often called xe2x80x9cperformance indicators.xe2x80x9d Further, this field is generally called xe2x80x9cprocessor performance instrumentation.xe2x80x9d
The number of hardware counters, however, is usually less than the number of performance indicators the tester needs to measure. For instance, there may be sixteen indicators to measure, but only two hardware counters, allowing the tester to measure only two of the sixteen indicators at a time. In order to measure the performance of the program with regard to all sixteen indicators, the tester must run the program multiple times. In this example, the tester must run the program eight times (sixteen indicators divided by two counters) to measure the performance of the program with respect to all the sixteen indicators. This procedure is inconvenient and time consuming.
One solution to this problem would be to have as many hardware counters as performance indicators to measure. Then, the tester could measure all the indicators with one run of the program. Added hardware counters, however, would increase the cost of the processor. Thus, it is desirable to count all the performance indicators during a single run of a program without adding more hardware counters to the processor.
In accordance with methods and systems consistent with the present invention, an improved processor performance instrumentation system is provided that allows a software tester to measure more performance indicators than there are hardware counters during a single execution of a tested program. The improved processor performance instrumentation system accomplishes this by xe2x80x9cmultiplexingxe2x80x9d performance indicators while executing the tested program. In effect, methods and systems consistent with the present invention extend the abilities of the limited number of hardware counters to allow them to measure a number of performance indicators otherwise not allowed during one execution of the tested program.
In accordance with methods consistent with the present invention, a method is provided in a data processing system for running a tested program. In accordance with this method, while the tested program runs, the method selects one of a plurality of performance indicators and instructs a processor to initialize a performance counter. Methods consistent with the present invention instruct the processor to measure the selected performance indicator and record measured data from the performance counter when a predetermined time period has expired after instructing the processor to measure. Finally, methods consistent with the present invention repeat the steps of selecting one of the performance indicators, instructing the processor to initialize the performance counter, instructing the processor to measure the selected performance indicator, and recording the measured data such that each of the predetermined plurality of performance indicators is measured by the performance counter.
In accordance with systems consistent with the present invention, an apparatus is provided containing a memory and a processor. The processor contains a performance instrumentation counter. The memory contains a tested program and a multiplexing application. The multiplexing application contains first code to run the tested program. The multiplexing application contains second code to select one of a plurality of performance indicators, and third code to instruct the processor to initialize the performance counter. The multiplexing application also contains fourth code to instruct the processor to measure the selected performance indicator and fifth code to record measured data from the performance counter when a predetermined time period has expired after instructing the processor to measure. Finally, the multiplexing application contains sixth code to repeat selecting one of the performance indicators, instructing the processor to initialize the performance counter, instructing the processor to measure the selected performance indicator, and recording the measured data such that each of the predetermined plurality of performance indicators is measured by the performance counter.
The summary and the following detailed description should not restrict the scope of the claimed invention. Both provide examples and explanations to enable others to practice the invention.